**Aeluma and Sumitomo Chemical Advanced Technologies (SCAT) partner to accelerate photonics wafer production for AI datacom, leveraging non-InP substrates to bypass indium phosphide supply constraints.**
Aeluma Inc of Goleta, CA, USA, a specialist in scalable technologies for AI, mobile, defense, and quantum, has executed an agreement with Sumitomo Chemical Advanced Technologies (SCAT) of Phoenix, AZ, USA, a subsidiary of Japan’s Sumitomo Chemical Co Ltd, to accelerate development and production of photonics wafers for the AI datacom market. The partnership initially leverages existing metal-organic chemical vapor deposition (MOCVD) capabilities at SCAT’s manufacturing facility, with a path for future capacity expansion.
Aeluma’s large-diameter non-indium phosphide (non-InP) photonics platform combines best-in-class materials with mass-market microelectronics manufacturing. With InP substrates in short supply and geopolitical risks adding uncertainty, alternative approaches are needed for high-performance photonics components such as photodetectors and lasers. Traditional InP manufacturing uses 100mm substrates; while 150mm InP lines are emerging, new fabs require time and resources to qualify, and InP substrates remain expensive and scarce. Aeluma’s heterogeneous integration leverages readily available non-InP substrates, including 150mm gallium arsenide (GaAs) and 200–300mm silicon (Si).
Beyond the SCAT partnership, Aeluma complements its in-house MOCVD capabilities by working with established large-volume GaAs and Si foundries for component fabrication, eliminating dependence on new fab buildouts. SCAT produces epitaxial wafers in Phoenix for optical communications, smartphones, wireless, and automotive industries.
“SCAT is an ideal partner to pair with Aeluma’s in-house MOCVD, capable of producing wafers of any size, including 150mm, 200mm, and 300mm substrates,” said Aeluma founder & CEO Jonathan Klamkin. “We have been working with SCAT for several years. This new agreement aims to strengthen our relationship and set the stage for accelerated development, qualification, production, and future potential expansion.”
SCAT president & executive officer Dr Ken Campman noted, “Demand for epitaxial wafers for photodetectors and lasers has grown significantly, but InP substrate supply is limiting development. Aeluma’s technology is a promising solution for the datacom market and may impact other markets as well.”
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Ceva and LG Electronics have partnered to remove a key barrier to ultra-wideband (UWB) adoption by integrating a complete radio, baseband, and software stack into a production system-on-chip (SoC), targeting semiconductor companies seeking precise ranging, positioning, and sensing for automotive, industrial, and consumer devices. Their joint platform combines Ceva-Waves UWB baseband intellectual property and software with an RF front end developed by LG Electronics’ SoC Center, designed for TSMC’s 22-nanometer process. This silicon-ready solution reduces interface validation, physical-design work, and performance tuning compared to sourcing radio and baseband separately, addressing challenges like precise timestamping, interference, multipath reflections, and non-line-of-sight conditions while keeping power and area low for battery-powered devices. Ceva’s next-generation architecture supports IEEE 802.15.4ab, improving extended-range and non-line-of-sight ranging, interference resilience, new channels, and UWB radar sensing—expanding UWB beyond phone-assisted item finding and vehicle digital keys to secure passive entry, occupant detection, factory tool tracking, and spatially aware smart-home controls. The business model licenses Ceva’s IP, allowing customers to embed UWB in differentiated SoCs alongside processors and security engines, with LG contributing RF expertise and process-specific implementation. A major U.S. semiconductor supplier has already adopted the solution, providing early commercial validation. ABI Research expects annual UWB device shipments to rise from 597 million in 2026 to nearly 1.18 billion by 2030, and this validated RF-to-software platform can help supply meet demand, increase competition, and bring precise spatial awareness to more edge devices.
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Penn State University and UK-based Battalion Advanced Technology have launched a research collaboration worth up to $6 million to develop advanced semiconductor platforms and high-temperature materials for next-generation energy, transportation, aerospace, and industrial systems, with direct implications for national security. Led by Penn State’s Materials Research Institute (MRI), the two three-year agreements, effective July 16, address critical materials challenges: integrating advanced semiconductors like gallium nitride (GaN) with high-performance substrates such as diamond and aluminum nitride to improve thermal and electrical performance, and developing durable, oxidation-resistant alloys for extreme environments including hypersonic flight. Battalion Advanced Technology, focused on dual-use next-generation materials, will provide up to $1 million per year per project. The semiconductor project, led by distinguished professor Joan Redwing, explores atomically thin interlayers to minimize crystalline defects and interfacial thermal resistance, enabling GaN growth on traditionally incompatible high-thermal-conductivity substrates. Co-principal investigators include MRI director Joshua A. Robinson, Adrianus van Duin, and Chen Chen. “This collaboration allows us to apply that breadth to two complex materials challenges with direct implications for US technological leadership and national security,” said Robinson. US Senator Dave McCormick noted the collaboration strengthens Pennsylvania’s role as a hub for American innovation in semiconductors, aerospace, and defense. The work leverages Penn State’s interdisciplinary materials research community and specialized facilities. This partnership targets dual-use semiconductor and materials science advances critical for defense and strategic industries.
CAST has introduced TCPIP-100G, a synthesizable intellectual-property core that implements a complete TCP/IP stack in hardware for ASICs and FPGAs, enabling autonomous 100 Gbps transmission and reception without host processor dependency. This core handles connection management, retransmission, flow, and congestion control entirely in hardware, supporting up to 32,768 simultaneous sessions configured at synthesis time. It operates as client or server, with base features including IPv4, ARP, ICMP, VLAN tagging, checksum generation, and jumbo frames. Options add DHCP client, out-of-order reassembly, UDP stack with IGMPv3 multicast, and a separate path for other IP traffic. Designers can choose cut-through mode for low latency or store-and-forward for integrity. Integration uses AXI4-Stream, AXI4-Lite/APB3, and AXI4 external memory interfaces, with independent clock domains. The core is independent of external memory technology, MAC, and PHY, and deliverables include synthesizable Verilog RTL or FPGA netlist. By offloading the full TCP stack to dedicated logic, TCPIP-100G makes latency more deterministic, frees CPU cores, and reduces data movement overhead—critical for AI/HPC clusters, hyperscale infrastructure, SmartNICs, and NVMe-over-TCP storage. While implementation results (area, frequency, power, throughput) are not yet published, the core represents a shift from software-based networking to a configurable hardware building block. Source: CAST, September 8, 2026.
Samtec is leveraging the AI Infra Summit 2026 and ECOC 2026 to demonstrate that high-speed copper and optical interconnects, not just faster accelerators, will determine next-generation AI infrastructure performance. At the AI Infra Summit (Sept 15–17, Santa Clara, booth 304), Samtec will showcase PCI Express 5.0 over FireFly optical cable assemblies, Si-Fly HD 224-Gbps PAM4 co-packaged and near-chip systems, and early 448-Gbps PAM4/PAM6 technology. The centerpiece is the Si-Fly HD CPX architecture—an electrically pluggable platform for co-packaged copper and optics fitting a 95×95 mm or smaller substrate. Its SFCM connector mounts directly to the package substrate, mating with Samtec’s SFCC cable assembly or compatible optics. This design avoids ball-grid-array breakout loss and long PCB traces, enabling a complete passive direct-attach-copper channel at 224 Gbps. Signal integrity becomes critical at 224 Gbps; shortening the electrical path preserves quality while giving architects flexibility to use copper for short reaches and optics for longer distances. Technical presentations by Matt Burns will address combining copper and optics in 224/448-Gbps systems and a practical route to 400G AI scale-up and scale-out implementations. At ECOC 2026 (Sept 21–23, Málaga), Samtec will join the Optical Internetworking Forum’s live interoperability demo with 39 member companies, proving multivendor components can work together—essential for AI infrastructure where no single supplier covers the entire data path. Samtec’s broader message: AI’s next performance gains depend on moving data efficiently, not just calculating faster. By demonstrating dense copper and optical systems with pluggable architectures
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SEMI joins ReSiLient consortium to strengthen Europeâs silicon and SiC raw material value chains
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SEMI has joined the ReSiLient consortium to strengthen Europe’s silicon (Si) and silicon carbide (SiC) raw material value chains, addressing a critical semiconductor supply chain bottleneck and advancing global resilience. Kicking off in 2026, the €9.57 million, 48-month Horizon Europe Innovation Action (Grant No. 101294649) brings together 18 partners from nine European countries. SEMI Europe will lead Work Package 8 on social acceptance, dissemination, communication, and standardization, driving stakeholder engagement across at least 10 EU member states and anchoring activities around SEMICON Europa 2026 in Munich (10–13 November).
The project targets four strategic objectives: mapping critical dependencies on imported Si and SiC feedstocks; developing primary (domestic minerals like olivine and aplite) and secondary (industrial waste streams) production routes using hydrometallurgical leaching, hydrogen plasma refining, and carbothermic conversion at pilot scale; qualifying project-produced materials for real semiconductor manufacturing via Czochralski crystal growth and SiC boule production, benchmarked by end-users STMicroelectronics Silicon Carbide AB and Infineon Technologies; and defining commercial pathways, IPR frameworks, and regulatory compliance for scale-up.
“Securing Europe’s access to silicon and silicon carbide is a strategic industrial imperative,” said Laith Altimime, president of SEMI Europe. “ReSiLient tackles critical raw material bottlenecks at the foundation of Europe’s semiconductor and power device industries.” The consortium includes Sintef, Wacker Chemie, Topsil Globalwafers, MEMC Electronic Materials, SCR-Sibelco, and others, spanning the full microelectronics value chain.
Semiconductor product realization requires preserving engineering state continuity across intent, design, fabrication, qualification, and lifecycle—not just completing sequential stages—according to a new framework that reframes development as a progression through trustworthy engineering states. This insight addresses the search intent of engineers and executives seeking to improve AI chip, memory, and heterogeneous integration reliability by moving beyond traceability to deeper relational integrity.
The article introduces three core concepts: **state realization** (creating the next trustworthy engineering state), **state continuity** (preserving relationships between states), and **engineering continuity** (maintaining those relationships across the lifecycle). Traditional development organizes work into stages—design, manufacturing, test, qualification—but a product changes engineering state at each transition: from intent to prediction, to physical hardware, to measured evidence, to qualified status, to yield/repeatability, to release, and finally to lifecycle behavior. The critical challenge is not whether each stage succeeds, but whether the meaning of each state remains connected to its predecessors.
Qualification is a key example: a device that passes reliability tests should remain linked to design assumptions, predicted behavior, physical structure, and manufacturing history. A failure that cannot be traced backward creates learning friction. Similarly, yield is not just a manufacturing metric but evidence of whether the intended product state can be repeatedly realized across variation. Field data gains engineering value only when it can reconnect to the as-built and as-qualified state of the shipped product.
The problem intensifies with heterogeneous integration—AI packages combining compute chiplets, HBM, optical engines, and advanced substrates accumulate more engineering states and transitions. Local optimization is insufficient; preserving state continuity across domains is essential. The article emphasizes that the semiconductor industry does not lack data, but lacks the engineering relationships that give data meaning across state changes.
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Jensen Huang declares AGI has arrived with OpenAI's GPT-6 Astra trained on over 100,000 Nvidia Grace Blackwell NVL72 systems, promising 400,000 more GPUs, while OpenAI chief scientist Jakub Pachocki warns of an assurance gap—highlighting the tension between infrastructure-driven momentum and deployment safety in the AI chip and data center sectors.
The article examines Huang's claim as an industrial statement rather than a scientific verdict. AGI—artificial general intelligence capable of human-level reasoning across domains—lacks a universal test. GPT-6 Astra shifts from next-token prediction to agentic operation: decomposing objectives, calling tools, writing code, and coordinating parallel attempts. The 400,000-GPU commitment supports reinforcement learning, synthetic data generation, and massive inference workloads, turning compute into search depth and experimentation.
However, scale multiplies exposure. Agents capable of cybersecurity work may also discover vulnerabilities. Pachocki's caution reflects that no lab has demonstrated alignment strong enough for indefinite scaling. Nvidia sells the substrate of the boom; OpenAI bears deployment responsibility. The practical question is whether institutions can predict, constrain, and audit systems whose autonomy grows with compute.
The article concludes that governance must become as measurable as performance, with thresholds tracking autonomous task duration, cyber capability, replication, and deception. Independent evaluations tied to enforceable limits are needed. Both Huang and Pachocki may be right: infrastructure is arriving rapidly, but adequate brakes are missing.