Apple's first foldable iPhone could arrive later than some market expectations, with supply chain sources indicating the device may not reach consumers until early 2027, pushing back the launch schedule for the company's entry into the foldable smartphone...
Google released the final version of Android 17 and Wear OS 7 on Tuesday, arriving first on Pixel devices alongside a Pixel Drop. The update emphasizes AI features, including the music-generation model Lyria 3, the multimodal Gemini Omni, and speech-to-translation tools for Pixel 10a with AudioLM. This underscores Google’s strategy to showcase its AI technology, contrasting with Apple’s upcoming AI upgrades to Siri and iOS 27.
Key features include Android Quick Share now compatible with Apple’s AirDrop on older Pixel 8a and 9a devices. Gemini Omni enables conversational video editing, while Lyria 3 lets users create music from text or images in the Gemini app. Pixel 10a gains improved speech-to-speech translation via AudioLM. Other phone features include recording personalized outgoing audio messages and expanding “Take a Message” to more global markets.
The Pixel Drop adds emergency detection to the Google Pixel Watch, automatically contacting emergency services and selected contacts if it detects a car crash, fall, or lack of pulse. Android 17 introduces a “bubble bar” UI for organizing and quickly accessing recent apps at the bottom of the screen, speeding up multi-app workflows. A new feature allows simultaneous selfie and screen recording for reaction videos for social media.
Parental controls and security are enhanced with “Mark as Lost” in Find Hub, Live Threat Detection, screen time limits, and content-filtering tools settable with a PIN without a Google account. A foldable gaming mode offers a 50/50 layout with a dynamic game pad.
Wear OS 7 brings live updates from phone apps mirrored to the Pixel Watch, better integration with upcoming AI glasses and headphones, and future Gemini Intelligence features like personalized widgets via description and “Personal Intelligence” using Google apps and chat history. Battery life improves by up to 10%, and multistep automation is added.
At HPE Discover 2026 in Las Vegas, CEO Antonio Neri delivered a keynote packed with announcements, with a heavy focus on networking and AI, as Juniper becomes fully integrated. Key highlights include:
- **HPE Juniper Networking** is now part of HPE AI Data Center Solutions. New switches: QFX5252 (scale-up, UALink over Ethernet, liquid-cooled, dual Broadcom Tomahawk 6), QFX5250 (scale-out, 102.5Tbps), PTX12000 (800Gbps routing, ZR/ZR+ optics), SRX4700 (quantum-safe 1.4Tbps firewall), MX301 (1.6Tbps inference edge router), and QFX5140 (16Tbps inference switch). HPE Networking CX switches can now be managed by HPE Mist.
- **AI and Compute**: HPE ProLiant Gen12 (DL394 Gen12 with NVIDIA), AMD Helios AI rack solution, HPE Private Cloud AI with NVIDIA platform and HPE Alletra Storage MP X10000 (AI-native file/object storage). HPE also announced AI Factory at Scale, Sovereign AI, and confidential computing standard across its AI Factory with NVIDIA Vera-based systems.
- **Software and Services**: HPE CloudOps extends Morpheus for broader ecosystem and VMware legacy footprint. HPE Agentic Enterprise manages shadow workforce with AI agent governance. HPE Marvis actions bring conversational AI to networking. HPE GreenLake intelligence uses agentic AI for operations optimization.
- **Customer Cameos**: Dallas Cowboys using HPE for AI, Vultr for next-gen AI build-out, and Siemens Energy for predictive failure.
The keynote underscored HPE’s emphasis on networking as the lead story, distinguishing it from competitors like Dell, which focused on compute. NVIDIA was a significant partner but absent from the stage. HPE positions itself as a networking company that also does AI compute.
At the 2026 VLSI Symposium, Intel Foundry provided an update on its process technology roadmap, focusing on the maturation of Intel 18A, the introduction of Intel 18A-P, and advanced research beyond gate-all-around (GAA) transistors. Intel’s strategy combines manufacturing execution with differentiated technologies to strengthen its foundry position.
Intel 18A, featuring RibbonFET GAA transistors and PowerVia backside power delivery, is now ramping in two U.S. fabrication facilities, with defect density declining ahead of projections. It is already powering multiple client products, with data center applications expected soon.
Intel 18A-P, the first performance-enhanced derivative, introduces new transistor options, improved power delivery, and enhanced thermal characteristics while maintaining backward compatibility. Based on a fully routed Arm core test vehicle, it offers up to 18% lower power consumption at iso-performance and about 9% higher performance at iso-power. Thermal resistance improves by 20–40%, and via resistance on critical interconnect layers decreases by 10–30%. A dual-contact Power Boost structure combines front-side and backside contacts via PowerVia to reduce parasitic resistance and improve current delivery. New intermediate threshold-voltage (Vt) options provide design flexibility, with 33% tightening of skew corners and reduced process variation.
Thermal management innovations include enhanced conductivity and EDA-driven optimization for power-dense AI and HPC workloads. Combining backside power delivery with GAA transistors yields approximately 10× dynamic voltage droop reduction, 5–6% frequency improvements, or over 15% dynamic power reduction, plus routing simplification and area efficiency.
Beyond current production, Intel presented research on Complementary FETs (CFETs) stacking PMOS and NMOS vertically, with a monolithic CFET inverter at 45 nm contacted poly pitch. A ruthenium-based interconnect architecture with air-gap integration achieved about 35% capacitance reduction versus copper. Additionally, integration of gallium nitride (GaN) power devices with silicon CMOS logic on 300 mm wafers aims to improve system efficiency and reduce cost.
Collectively, these announcements highlight Intel Foundry’s dual focus on near-term manufacturing execution (18A ramp, 18A-P performance boost) and long-term innovation (CFETs, advanced interconnects, heterogeneous integration), positioning Intel as a leading developer of next-generation semiconductor process technologies.
SiMa Launches Agentic Development Environment for Physical AI
PowerUP Circuit Lab: ADI s EVAL-LT7170-1-AZ Evaluation Board
Enkris Semiconductor, a pure-play gallium nitride (GaN) epitaxial wafer foundry based in Suzhou Industrial Park, Jiangsu, China, has unveiled a high-speed, low-power micro-LED optical interconnect product. This development comes as data centers face soaring bandwidth demands from artificial intelligence and computing power growth, driving a shift from copper to optical interconnects for short-distance links within servers and racks.
Traditional micro-LED optical interconnects use sapphire substrates, which suffer from low bandwidth and high drive current density. Enkris has developed 8–12-inch GaN-on-Si micro-LED light-source products that achieve a 3dB bandwidth of 1.6GHz at a current density of 500A/cm², with power consumption below 1pJ/bit. The company leveraged its GaN epitaxy expertise and a CMOS-compatible micro-LED process flow to optimize epitaxial structures, material quality, and device design. By suppressing the quantum-confined Stark effect (QCSE) in the quantum wells, carrier recombination rate is enhanced. Reducing active region area lowers device capacitance and minimizes RC delay.
In collaboration with Professor Lu Shulong's research group at the Suzhou Institute of Nano-Tech and Nano-Bionics, Chinese Academy of Sciences, Enkris achieved the 1.6GHz cut-off frequency under ultra-low current injection, placing it at an industry-leading level. The 8”/12” micro-LED on silicon enables integration on advanced-node CMOS via mature wafer-to-wafer or die-to-wafer bonding. This technology is compatible with existing hardware architectures and protocols used in high-bandwidth memory, filling a gap in short-range transmission. With low power consumption, low heat generation, and no electromagnetic interference, it is expected to accelerate adoption of micro-LED short-distance interconnects in data centers.
YMIN SLX Hybrid Supercapacitors Replace Batteries in Space-Constrained Designs
Suppliers 16 June 2026 – Element Six (Oxford, UK), a synthetic diamond materials firm and part of the De Beers Group, and Tokyo-based Orbray Co Ltd have announced the next phase of their partnership to deliver wafer-scale single-crystal diamond (WSC). They have established a reproducible process for 3-inch WSC diamond, marking a significant improvement in size, uniformity, and manufacturability over conventional single-crystal diamond. Development of larger 4-inch substrates is underway. Meanwhile, 2-inch wafers optimized for epitaxial applications are nearing finalization, and 2-inch wafers for thermal bonding applications are being prepared for volume production at Element Six’s chemical vapour deposition facility in Gresham, Oregon.
The collaboration focuses on advancing wafer size alongside manufacturing maturity to accelerate adoption of WSC diamond across 6G wireless components, power and RF electronics, sensing, thermal management, and quantum technologies. These developments represent a transition from R&D to scalable implementation, with the companies now refining production processes to support operational ramp-up for volume manufacturing at industrial scale.
Element Six CEO Siobhán Duffy stated that the partnership builds on shared strengths in innovation and quality, translating into tangible progress towards wafer-scale single-crystal diamond at the quality and volumes needed by industrial customers. Orbray president & CEO Riyako Namiki noted that the milestones achieved so far are meaningful steps in expanding commercial use of single-crystal diamond, advancing material capability alongside the manufacturing volumes required for demanding applications.
The article introduces the Vertical System EM Corridor (VEMC) as a new paradigm for AI packaging, moving beyond traditional flat, planar architectures. As AI platforms demand higher bandwidth, power density, and heterogeneous integration, packages are no longer just flat routing surfaces but must become vertical realization environments.
The VEMC is the physical path where signal integrity, return current, power integrity, thermal and mechanical behavior, and geometry interact. In current systems, this corridor is largely lateral; future large AI systems require vertical extension. Glass substrates and through-glass vias (TGVs) enable this, offering dimensional stability and fine interconnect scaling. However, vertical routing alone is insufficient—every high-speed signal needs a controlled return path via nearby ground-reference TGVs to avoid impedance discontinuity and signal degradation.
A future AI package may integrate compute, memory, power delivery, and optical transition zones across multiple vertical regions. Traffic will be hybrid: short, dense electrical links (GPU-to-HBM) and longer paths better suited for optical conversion. Power delivery also becomes vertical, moving closer to silicon via chiplet-proximate architectures, with controlled vertical paths and embedded decoupling. Optical transition zones are selectively introduced where distance and bandwidth justify conversion, requiring careful electro-optical realization.
The VEMC differs from 2.5D/3D packaging, which focus on physical placement; VEMC emphasizes the full realization path where electrical, optical, power, thermal, and mechanical behaviors must remain coherent for trusted system output. The industry is moving from integration to trusted realization—ensuring that a vertically integrated package operates stably, reliably, and scalably under real conditions.
This matters now because AI hardware forces packaging to become system architecture, with HBM, GPU-to-GPU, optical I/O, power, and thermal all converging into one physical problem. The future AI package will not just be wider but deeper, and success will depend on making the vertical realization path trusted at scale. The next frontier is not a single material or device but the ability to control the entire vertical electromagnetic corridor.
RISC-V Silicon in the Jungle Could Save the Amazon
PCIM 2026: Infineon’s Peter Wawer on Grid Resilience, Solid-State Circuit Breakers, and the Path to 800V Data Centers
ASML, TSMC, and imec have demonstrated a major advance in the effort to bring two-dimensional (2D) semiconductor materials from research laboratories into high-volume semiconductor manufacturing. At the 2026 IEEE/JSAP Symposium on VLSI Technology and...
Two Brazilian researchers from the University of São Paulo, professors Marcelo Zuffo and Laisa Costa, unveiled the "Internet of Trees" at the RISC-V Summit Europe 2026. This system uses open-architecture RISC-V microprocessors to create a connected sensor network serving as a digital nervous system for the Amazon rainforest. The project aims to address the lack of reliable, real-time data on forest health, crucial since the Amazon is the world's largest land-based carbon sink and faces a critical climate threshold at 25.4°C, beyond which trees may die.
Unlike traditional remote sensing blocked by the canopy, the team proposes a low-power network of microsensors inside the forest. The core is the PULGA microcontroller, built on the open RISC-V architecture to avoid proprietary "black boxes." It consumes 13.8 milliwatts, includes cybersecurity, and operates on a Swarm OS with Zephyr. Sensor nodes process data locally using neural networks, sending only alerts via LoRa networks up to 40 km to cloud servers, saving bandwidth and battery.
Powering millions of sensors deep in the Amazon is a challenge due to no light or wind. Costa is developing energy-harvesting chips like "Flea," and the team mimics parasites to extract energy directly from trees. Biodegradable materials and hydrogen batteries ensure sensors decompose naturally.
The project is funded by a Brazilian law requiring 1% of oil profits for research. Applications include carbon credit verification, biodiversity monitoring, and detecting illegal logging, mining, or poaching by tracking humidity and CO2 changes. The network also aims to create a digital twin of the Amazon with LLM dashboards for real-time reports. Using 3D printing via the PocketFab project, the team can manufacture PULGA nodes on-site, reducing supply chain reliance. The ultimate goal is to provide a concrete, efficient measurement system to prevent crossing a no-return climate point.
AI chip startup Tensordyne has taped out its data center inference chip, claiming an order-of-magnitude improvement in power efficiency over leading GPUs. The company says its systems achieve 17× the tokens per second per Watt versus an Nvidia GB300-based system, or 13× the tokens per second per rack.
Tensordyne co-founder and VP of AI Gilles Backhus said the two biggest challenges in data center AI inference are speed and cost. The chip is built on TSMC 3nm, consumes 300W per package, and offers 2.1 PFLOPS (dense FP8) with 144 GB HBM3e. Its 72-chip Napier server is air-cooled at 30kW, occupies a quarter rack, and includes 10 TB of HBM. Each full rack of four Napier servers (288 chips) delivers 608 PFLOPS dense FP8, 74 GB SRAM, 42 TB HBM, and consumes 120 kW.
The performance advantage comes from Tensordyne’s proprietary Pareto number system based on logarithmic number system (LNS), with dedicated hardware acceleration for efficient addition in the log domain. The software stack handles conversion transparently, supporting PyTorch and Triton. The chip has 5× the SRAM of a current-generation GPU (256 MB), reducing HBM accesses. It uses a cell-based network-on-chip (NoC) to reduce tail latency, critical for fast decode with mixture-of-experts models. Single-hop chip-to-chip latency is under 1 microsecond.
Tensordyne partnered with HPE Juniper on the system’s scale-up interconnect and chassis. Systems are due to start shipping by Q2 2027, with a development cloud available by end of 2026.
Editor’s note: Tensordyne simulations show rack-scale systems achieving 3 million tokens per second per megawatt versus 183,000 for NVL72-GB300 racks, and 363,000 tokens per second per rack versus 27,400, based on InferenceX benchmarks for DeepSeek-R1-670B at FP4.
AMD CEO Lisa Su. Credit: DIGITIMES The AI data center buildout is driving demand for high-performance computing (HPC) and networking chips, sending the global IC substrate industry into a new growth cycle. Order visibility now extends two to three years, prompting Taiwan's three leading IC...
PicoJool Inc of Palo Alto, California is introducing 200G vertical-cavity surface-emitting laser (VCSEL) products with bandwidth exceeding 37GHz, targeting hyperscale AI data centers. The company develops optical chips and modules for high-bandwidth, low-cost connectivity. Sampling of chip-level products begins in third-quarter 2026, including quad 100G, quad 200G and 32x50G NRZ micro-VCSELs for slow and wide applications. PicoJool is already collaborating with system startups and hyperscalers to define next-generation pluggable, near-packaged optics (NPO) and co-packaged optics (CPO) solutions for AI data centers.
VCSELs have been the backbone of data-center optical connectivity since 1996, valued for speed, reliability and cost efficiency. PicoJool claims its technology eliminates doubts about scaling to meet AI bandwidth demands. The 200G VCSEL products pave the way for optical links that are as inexpensive, compact and manufacturable as traditional copper connections, with a clear roadmap to 800G, 1.6T and 3.2T speeds.
A manufacturing partnership with WIN Semiconductor, the world’s leading VCSEL producer for 3D sensing applications that has shipped over a billion chips in the past decade, underpins the effort. PicoJool’s 200G designs and process recipes have been transferred to WIN and other foundries specializing in gallium arsenide (GaAs). Because GaAs-based VCSELs are unconstrained in production capacity, the company avoids supply bottlenecks that limit competing laser technologies. Founder & CEO Al Yuen stated, “Our partnership with WIN Semiconductor has been very fruitful as we get ready to release a series of VCSEL products for high-volume manufacturing.” Pat Gelsinger, general partner at Playground Global, commented, “By building on a GaAs supply chain that has already shipped billions of chips, Picojool has solved both sides of the equation: record bandwidth and the production scale to deliver it. That combination turns a lab achievement into an industry shift, creating a viable path from copper to optical at AI scale.”
PicoJool will begin sampling its 200G VCSEL products in third-quarter 2026, with a high-volume ramp expected in early 2027.
TSMC is accelerating its advanced packaging roadmap for AI chips, expanding CoWoS capacity while publicly disclosing new progress in glass substrate technology. The company is also signaling that next-generation packaging competition is shifting from CoWoS...
EE Times Asia is offering free samples of onsemi's Treo Analog and Mixed-Signal Platform, along with a limited-time incentive for engineers. The application period runs from May 11 to June 30, 2026. The first batch of qualified applicants will be announced around June 17, 2026, and the second batch within one week after the application closes. The first 20 engineers whose applications are reviewed and approved will each receive a $10 Amazon e‑gift card, in addition to the free hardware samples.
To apply, users must log in (new users must register as an EE Times Asia member first), then click the "Apply Now" button on the event page and submit the required information. The product sponsor will review the submissions and determine the final list. The qualified list will be announced in the introduction column of the page. After the announcement, winners should check their email and provide a real and valid delivery address. Inaccurate or incomplete addresses will result in no shipment.
All application information is shared with the sponsor for review and screening. The sponsor may send relevant information based on applicants' interests. If contact is not possible using the provided information, the applicant will forfeit their qualification. The final interpretation right belongs to EE Times Asia.
The product being sampled is onsemi's Treo, an analog and mixed-signal platform built with reusable analog, digital, and power IP blocks. It supports power management ICs, sensor interfaces, communication devices, and a full portfolio of standard products. Multiple products are already sampling, with LDOs and regulators available for project trial. Units are limited and allocated on a first‑come, first‑served basis.
Participants are encouraged to share the event with colleagues. Aspencore reserves the right of final interpretation for the lucky draw. For questions or product offerings, contact EE Times Asia.
Designing Scalable Firmware
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In embedded systems, firmware governs operational logic, coordinates peripherals, and manages hardware resources. As designs grow complex and hardware evolves, scalability is critical: systems must adapt without full rewrites, support diverse hardware, enable rapid secure changes, and maintain stability. Benefits include reduced long-term costs and increased flexibility.
Key design fundamentals: define requirements (functionality, performance, security, quality); design architecture and interfaces; implement security measures; monitor throughout the lifecycle. Main features of scalable firmware include modular architecture—code broken into independent, reusable modules; Hardware Abstraction Layers (HAL) separating application logic from hardware for platform portability; over-the-air upgradability; and versatility for multiple interfaces and protocols.
Modularity is foundational: separating drivers, middleware, and application logic allows upgrades or replacements without system rewrites and promotes code reuse. Hardware abstraction via uniform interfaces makes firmware independent of specific microcontrollers (e.g., STM32 vs. ESP32), easing portability and maintenance. Testability is linked: modular code enables unit and integration tests, reducing regressions and improving robustness.
Common architectures include layered designs (hardware, services, application) communicating through defined interfaces, allowing modifications without impacting the whole. For complex systems, a real-time operating system (RTOS) organizes software into independent tasks with priorities, suitable for handling many simultaneous events (sensors, communications, actuators). Event-driven architecture is preferred over polling for responsiveness and lower CPU load.
Hardware resource management is vital: careful memory handling (pre-assigned buffers, object pools) ensures stability. Modular drivers and standardized interfaces for peripherals and I/O allow adding devices without rewriting logic. Efficient use of timers, interrupts, and scheduling balances CPU load while maintaining flexibility by separating hardware management from application logic.
Development tools: modular build systems and flexible configurations adapt code to different platforms. Automation of build, testing, and firmware generation speeds verification. Static analysis and simulation catch issues early. Unit and integration tests verify modules and interactions; real hardware tests evaluate performance, stability, and power consumption. Monitoring metrics like response time, memory usage, and test coverage ensures quality.
Applications: scalable firmware is in high demand in industrial IoT (IIoT) for upgrading multiple machines simultaneously, as well as in consumer electronics.