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Dr. Wei has served as CEO of Easy-Logic since 2020, focusing on building a strong operational foundation for the company. Previously, as CTO, he led the development of the core algorithms and tool architecture for the flagship product EasylogicECO, seamlessly aligning EasylogicECO technology with user needs. Dr. Wei holds a PhD in Computer Engineering from The Chinese University of Hong Kong and an MSc and BSc in Computer Science and Technology from Tsinghua University. Tell us about your company? Easy-Logic Technology is a specialist provider of Functional ECO solutions, founded in Hong Kong in 2013. Our core team grew out of the EDA laboratory at The Chinese University of Hong Kong, and our core algorithms won first place in the CAD Contest at ICCAD for three consecutive years (2012–2014). Building on this research, we develop industrial-grade EDA software. Our Functional ECO technology enables a breakthrough incremental design flow for the ASIC industry. We now serve nearly 100 paying customers, including leading semiconductor design companies in mainland China, Taiwan, the United States, and South Korea. What problems are you solving? We address late-stage logic and functional changes in chip design—known as Functional ECO. Industry data indicates that over 86% of ASICs require two or more tape-outs, with logic and functional issues among the leading causes of tape-out failure. ASIC development involves complex stages such as logic synthesis, DFT, and placement&routing. Unexpected bugs, specification changes, or evolving customer requirements can necessitate functional changes late in the process, and re-running the entire design flow can take months and cost millions of dollars. The key challenge is how to make a small, precise functional change without restarting the full flow—that is the purpose of an Engineering Change Order (ECO). Our flagship product, EasylogicECO, applies logic changes directly to the netlist at the current design stage and automatically generates a smaller, optimized patch of logic. This can reduce turnaround time from months to days and integrates seamlessly into existing design flows. It helps preserve timing closure while saving time and engineering resources. Use cases include pre-mask ECO, post-mask ECO (metal ECO), and product revisions or upgrades. What application areas are your strongest? Our strongest area is time-critical Functional ECO for digital chip design—situations where functionality must be changed late in the process, deadlines are tight, and manual fixes are difficult. Examples include correcting issues in complex digital designs such as CPUs, GPUs, DPUs, and SoCs after RTL freeze but before tape-out, and making RTL-driven changes to digital and mixed-signal chips after tape-out. Many existing Functional ECO tools are add-ons to formal verification platforms rather than purpose-built ECO tools. Their capabilities can be constrained by the underlying verification technology, often resulting in long runtimes, limited automation,poor usability, and disappointing results. Functional ECO is often needed at a critical moment, the tool must be easy to operate, require minimal setup, work out of the box, and deliver high-quality results quickly—ideally in a single run. EasylogicECO was developed specifically for these needs. Its purpose-built flow and algorithms increase automation and improve both runtime and patch quality. Tests show it runs several times faster than traditional tools, while producing patches that are, on average, 30% better in quality; in some cases, the improvement exceeds 10×.This enables customers to resolve difficult chip-design issues quickly and efficiently. What keeps your customers up at night? As chip complexity grows and schedules tighten, design teams can no longer assume RTL will remain unchanged after freeze. First-pass tape-out success remains a major challenge, and a single logic bug found late can determine whether a product succeeds or fails. When an unexpected issue emerges, customers need to keep the project on schedule while minimizing risk and cost. ECO work is unpredictable. Manual ECO requires expertise, is error-prone, hard to debug, may need multiple iterations, and is generally suitable only for simple changes. Some conventional tools are slow, difficult to use, or produce unexpected results. A failed ECO can delay a project or jeopardize the product. Second, backend implementation must still converge. Even when an ECO is generated successfully, an oversized patch can make timing closure and physical implementation difficult. The process can also affect scan chains, low-power structures, or DFT constraints, Finally, the ECO window is often extremely short—sometimes just before tape-out or even after mask release. Engineers may have little opportunity for repeated iterations, so speed, ease of use, and first-run quality are essential. EasylogicECO is designed to address these challenges. Its proprietary, fully automated algorithms quickly generate smaller, optimized logic patches, with a streamlined user experience, short runtimes, and support for multiple design constraints—helping improve ECO success rates. Competitive landscape and differentiation Functional ECO is a highly specialized segment of the EDA market, with very few vendors offering automated solutions. In a market dominated by a small number of large vendors, we have established a differentiated position by focusing on logic-level changes late in the design process. Our technology approach is different. Tools on the market mainly are built as add-ons to formal verification platforms and are constrained by the characteristics of those platforms. EasylogicECO is built around algorithms designed specifically for ECO, delivering improvements in performance and efficiency. We also place strong emphasis on customer support. Although EasylogicECO can be integrated directly into an existing ASIC design flow, customers differ in their workflows and design practices. Simplifying tool usage and providing tailored engineering support are therefore important. We focus on two priorities: responding promptly to customer issues and delivering customized support as quickly as possible, so customers can complete ECO tasks with minimal delay and keep product development on schedule. In short, Easy-Logic follows a distinct approach in the specialized Functional ECO market. For chip-design companies worldwide, we offer a focused, reliable alternative for late-stage logic changes—without dependence on a single EDA vendor. What new features or technologies are you working on? At the late stages of chip design, ECO tasks often arise under severe time pressure, while conventional methods may struggle to deliver results efficiently. Customers increasingly expect not just a tool that can perform an ECO, but one that can produce high-quality results quickly and predictably. We continue to advance both our products and our overall design-flow capabilities to meet increasingly complex needs. We have introduced EasyAI ECO Suite, which integrates AI engines throughout the ECO workflow. Its first three intelligent engines are: Auto Partition intelligently divides very large circuits into solvable subproblems, reducing patch size by more than 20% on average and by as much as 90% in some cases. • Learning / I-Learning progressively searches for better structures across iterations, reducing patch size by more than 20% on average. • Smart Caching reuses results from previous runs and can reduce runtime by up to 80% in multi-iteration scenarios. The solution has been validated in real projects at several leading chip-design companies. It is designed to address key limitations of conventional ECO approaches in patch size, runtime, and timing accuracy. At the flow level, we are also expanding toward a comprehensive suite of incremental design tools. EasylogicECO currently supports Functional ECO, Scan Chain ECO, Low Power ECO, and Metal ECO. We are continuing to develop capabilities for Clock Tree ECO, Placement ECO, Timing ECO, and Routing ECO, with the goal of building an incremental design tool chain that covers the full range of late-stage chip changes. How do customers normally engage with your company? Customers typically work with Easy-Logic through software licensing. They first evaluate the tool in their own design environment to confirm that EasylogicECO meets their specific requirements. After a successful evaluation, the parties generally proceed with an annual license. Other flexible engagement models are also available and can be discussed based on each customer’s needs. Companies with Functional ECO requirements are welcome to contact us: Phone: 714-287-5154 Email: info@easylogiceda.com Website: https://www.easylogiceda.com/en Also Read: Demonstrating the EasyAI ECO Suite – An AI-Powered Functional ECO Solution at DAC 2026 Smarter ECOs: Inside Easy-Logic’s ASIC Optimization Engine Webinar Preview – Addressing Functional ECOs for Mixed-Signal ASICs Share this post via:
While AI is transforming nearly every industry, some of its most significant advances are happening inside the semiconductor factories building the chips that power it. If you design AI systems, those manufacturing advances directly influence your performance, efficiency, and path to market. The message from the recent Global Semiconductor Alliance European Executive Forum was clear: Scaling AI requires more than smaller transistors. You must also address power delivery, connectivity, advanced packaging, and supply chain resilience. These factors increasingly determine how effectively you can turn silicon innovation into system performance. According to a presentation by Prashanth Aprameyan, Intel Foundry supports this strategy on two fronts: Advanced process and packaging technologies that enable more capable systems, and AI-enabled manufacturing that improves quality and accelerates yield learning. Three forces shaping your designs Three AI trends are changing what you need from silicon. Agentic AI introduces multistep reasoning workloads that are less predictable than traditional computing. As you deploy autonomous agents, efficient power delivery and high-performance connectivity become essential to scaling their capabilities. Physical AI brings intelligence into edge devices and real-world systems. You need architectures that balance capability, efficiency, and cost, supported by manufacturing approaches that use automation and modeling to improve yield. Sovereign AI adds another consideration: where and how your chips are manufactured. Secure, resilient, geographically diverse supply chains support business continuity and national security requirements. Intel Foundry’s capabilities across North America, Europe, and Asia give you greater flexibility in choosing manufacturing locations. Scaling your entire system You are no longer limited to integrating every function onto a single chip. Chiplet architectures let you combine specialized dies, memory stacks, and accelerators into a system of chips. This modular approach helps you scale performance and select the technology best suited to each function. Transistor innovation remains essential. Intel 18A uses RibbonFET Gate-all-around technology to improve electrostatic control and support scaling beyond traditional FinFET architectures. Power delivery also matters. With PowerVia, Intel 18A routes power through the back of the wafer, separating power paths from frontside signal routing. This reduces resistance, voltage drop, and power delivery noise. Combined with high-density metal-insulator-metal capacitors, the architecture strengthens power integrity and supports more efficient use of chip area. You also need these improvements to remain economically practical. Intel Foundry balances backside power complexity with frontside lower-metal pitches that enable direct-print patterning, helping manage manufacturing costs while improving performance per watt. As your systems become more modular, communication between dies becomes critical. Universal Chiplet Interconnect Express, or UCIe, provides standardized, high-bandwidth, low-latency connections that simplify chiplet integration. Advanced packaging brings these elements together. Intel Foundry’s portfolio includes EMIB-T, Foveros, and Foveros Direct. EMIB-T incorporates power-transfer capabilities into its bridge structure and can remove the need for a full silicon interposer in many applications. Foveros Direct uses hybrid bonding to stack compute dies on optimized base dies, helping you balance performance, power efficiency, and total cost of ownership. How AI improves your manufacturing outcomes AI also helps address the complexity of manufacturing your designs. During design technology co-optimization, AI helps engineers explore large design spaces and evaluate tradeoffs among power, performance, and area. Intel Foundry’s factories collect nearly a billion images each week, generating petabytes of manufacturing data. Machine learning analyzes these images to detect defects, classify failure patterns, identify yield risks, and improve design rules. For your Intel 18A designs, these insights help surface potential layout issues earlier. Neural networks and ensemble decision trees help isolate root causes and accelerate defect resolution. You benefit from faster learning cycles and more predictable yield progression as technologies enter production. Digital twins and predictive maintenance monitor manufacturing equipment, identifying potential tool issues before they disrupt production and supporting continuous factory operations. Bringing your next system to market Your success depends on optimizing the entire platform. With advanced process technologies, packaging innovation, and AI-enabled manufacturing, you can build increasingly capable AI systems and bring them to market faster, more efficiently. Explore your options at intel.com/foundry or contact foundry.contact@intel.com. Also Read: Intel’s Open Software Blueprint: Why Production AI Needs More Than GPUs Data Center Energy Trends Force a Rethink of Chip Power Delivery Intel Foundry: AI performance now depends on the whole system Share this post via:
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gRPC-based solution enables cross-platform access to Pickering PXI and PXIe hardware while preserving existing driver investments Pickering Interfaces, a provider of modular signal switching and simulation solutions for electronic test and verification, has introduced Pickering Remote Gateway. The new gRPC-based software enables engineers to control Pickering PXI/PXIe products remotely from applications running on separate computers, across multiple operating systems and programming languages. Pickering Remote Gateway allows test hardware to remain close to the device under test or in a central lab rack while engineers run their applications from network-connected workstations. It supports automated validation, production test and distributed development, helping teams access shared test resources without requiring every application to run on the controller connected to the chassis. “Test teams increasingly work across different locations, operating systems and programming languages, but they still need access to the same physical hardware,” said Alexander Jaiboy, Software Manager at Pickering Interfaces. “Pickering Remote Gateway gives engineers more freedom to work with their existing PXI systems, keeping hardware where it is needed while allowing test applications to run remotely.” The software exposes Pickering driver APIs through a gRPC Device Server running on the host PC or embedded controller. Remote requests are passed to the local drivers, preserving existing hardware and driver investments. Only the host system requires Pickering drivers; client systems do not need the full Pickering driver stack installed. Pickering provides servers for Windows and Linux, together with Protocol Buffers (.proto) files that define the remote interface. Engineers can use these files to generate client code for environments that support gRPC and Protocol Buffers, including Python, C#, Go and Java. This gives teams greater freedom to use their preferred development tools and integrate instrument control into mixed software environments. Built on the open-source gRPC framework and HTTP/2 transport, Pickering Remote Gateway brings a modern service-based interface to PXI test systems. Test routines, user interfaces, analytics and orchestration can run separately from the instrument-control host, supporting distributed architectures and integration with cloud-hosted applications and automated development pipelines. All products supported by the Pickering PXI driver are supported by the gateway. Pickering modules can remain within mixed-vendor chassis configurations, with the gateway providing remote access to the supported Pickering hardware. About Pickering Interfaces Pickering Interfaces designs and manufactures modular signal switching and simulation products for electronic test and verification. Its PXI, LXI, and PCI solutions are used in test systems worldwide across automotive, aerospace and defense, energy, industrial, communications, medical, and semiconductor applications.
Discussions around TSMC’s vertical DRAM patents raise an intriguing question: could the world’s leading foundry eventually challenge established memory manufacturers? The curiosity is understandable. Patent disclosures involving vertical transistors and integrated capacitors show that TSMC is exploring architectures relevant to future memory scaling. But technical exploration and commercial market entry are different milestones, separated by enormous manufacturing and economic hurdles. Precision matters when interpreting the patent itself. “US @2022” does not uniquely identify a document. One relevant TSMC application, US20220359529A1, published in November 2022, describes a vertical-channel transistor integrated with a hybrid trench-and-stacked capacitor. Another, filed in May 2022 and published as US20230240066A1, places a capacitor directly above a vertical gate-all-around transistor. These disclosures should not be merged into a single architecture or treated as product announcements. Their significance is nevertheless real. They demonstrate exploration of ways to reduce memory-cell footprint and integrate storage structures vertically. They do not establish TSMC’s production readiness, investment commitment, or intention to sell commodity DRAM. A plausible interpretation is that such research preserves options for embedded memory, logic-memory integration, or future customer requirements. That remains an inference, rather than a disclosed commercial strategy. The broader competitive story concerns how DRAM can continue scaling. SK hynix has publicly identified both a 4F² vertical-gate platform and 3D DRAM as future directions. Crucially, these are related but distinct concepts: a smaller cell footprint does not automatically mean multiple active memory layers. Likewise, stacking completed DRAM dies in HBM differs from building vertically repeated cells within a memory array. For SK hynix, Samsung, Micron, and any prospective entrant, the decisive challenge is converting structural promise into reliable, affordable bits. A compelling cross-section is only the beginning. Engineers must make the transistor, capacitor, interconnects, and surrounding circuitry work together across large arrays, manufacturing variations, operating temperatures, and repeated production cycles. The first obstacle is electrical control. An access transistor must deliver enough current for fast operation while limiting leakage sufficiently to preserve stored charge. Dense vertical arrangements also make interactions between neighboring structures harder to manage. SK hynix’s research on bit-line shielding and back-gate control illustrates how much engineering can sit behind an apparently simple reduction in cell area. The second obstacle is capacitor integration. Shrinking the footprint does not remove the need for a readable charge-storage signal. Designers must balance capacitance, dielectric leakage, breakdown reliability, and fabrication complexity. Vertical geometry offers additional surface area, but it also demands consistent deposition, etching, and electrical connections in increasingly confined spaces. Every additional structural advantage introduces another integration problem that must be solved. The third obstacle is manufacturing economics. Additional layers can increase nominal density while adding process steps, inspection requirements, and opportunities for defects. Thermal budgets constrain which materials and fabrication sequences can coexist. Bonding approaches introduce their own alignment and interface requirements. The relevant commercial measure is therefore cost per usable, qualified bit, rather than the number of cells drawn into a proposed structure. This is why the patent discussion matters beyond speculation about TSMC. If conventional DRAM scaling becomes more difficult, architectural transitions could influence memory capacity, power consumption, supply economics, and the cost of computing. Yet higher density alone cannot guarantee greater bandwidth or lower system energy. Those outcomes also depend on peripheral circuits, interfaces, packaging, and how memory connects to processors. Bottom line: TSMC’s disclosures deserve attention as evidence of technical exploration. Their larger lesson is that future DRAM leadership will require architecture, materials, process integration, and manufacturing discipline to advance together. Established memory companies bring accumulated production experience; potential challengers may bring different integration strengths. The winners will be those that turn promising structures into dependable products at competitive cost. That is where 3D DRAM competition becomes consequential. Also Read: TSMC’s AI Expansion Signals a Broader Shift in Computing TSMC 2026 OIP Ecosystem Forum Summary From Cloud to Silicon: IC-Link and TSMC Open the Door Share this post via:
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News: Photovoltaics 30 October 2026 First Solar licensing CubicPVâs US patents for perovskite solar technology Cadmium telluride (CdTe) thin-film photovoltaic (PV) module maker First Solar Inc of Tempe, AZ, USA has signed a non-exclusive licensing agreement granting it access to the issued and pending US patents covering perovskite solar technology of CubicPV Inc of Bedford, MA, USA. The license further clears the path for First Solar to continue its development of PV devices built with a perovskite semiconductor for the US utility-scale, commercial and industrial, and residential markets, and applies to sales and distribution of those products domestically. First Solar, the largest solar manufacturer in the Western Hemisphere and the world's largest thin film producer, has invested over $2bn in thin-film R&D, including its efforts to advance its perovskite program. Investments include a new perovskite development line at its Perrysburg, Ohio, campus that produces small-form-factor modules featuring a perovskite semiconductor, allowing First Solar to meet key internal milestones in its perovskite development program, including initial-stage efficiency, stability, and manufacturability objectives. It is also investing in a larger pilot line â capable of producing modules equivalent in dimensions to its Series 6 module â in Ohio, which is expected to reach operational readiness in first-half 2027. “Commercializing the next generation of PV takes two things. It takes the technology development and manufacturing scaling work our R&D teams are focused on, and it takes freedom to operate, which is what this agreement helps secure,” says CEO Mark Widmar. “We’ve always believed intellectual property rights should be respected, and this is consistent with that. This is a new semiconductor technology with real disruptive potential, and we want to get it right.” CubicPV has spent over a decade developing, testing and fielding perovskite technology to build a body of foundational patents and intellectual property. Guided by a durability-first philosophy, it translates breakthrough science into demonstrated product performance, combining technical expertise with scaleable manufacturing processes to accelerate the commercialization of next-generation solar technology. “Access to intellectual property is vital as the industry begins commercializing perovskite and tandem technologies,” says CubicPV’s CEO Tim McCaffery. “First Solar's decision to license our IP is evidence of that shift and shows the relevance of our IP portfolio to the perovskite ecosystem.” First Solar operates the largest solar technology manufacturing and R&D footprint in the Western Hemisphere, with five fully vertically integrated manufacturing facilities operating in Alabama, Louisiana, and Ohio. A sixth operating facility, in South Carolina, onshores final production processes for Series 6 Plus modules initiated by the company’s international fleet. By the end of 2026, the firm expects to have invested over $5bn in American manufacturing and R&D infrastructure since 2019, and it expects about 17GW of US module manufacturing capacity by 2027. See related items: First Solar licenses Oxford PV’s patents for US markets First Solar acquires Swedish perovskite PV firm Evolar Tags: First Solar perovskite Visit: www.cubicpv.com Visit: www.firstsolar.com
News: Suppliers 30 October 2026 Wolfspeed launches transparent silicon carbide technology for AR and quantum computing Wolfspeed Inc of Durham, NC, USA â which makes silicon carbide (SiC) materials and power semiconductor devices â has announced the commercial introduction of its proprietary transparent silicon carbide (TSiC) technology, expanding the potential of SiC to enable next-generation augmented reality (AR), quantum computing and advanced optical applications. Building on over 35 years of silicon carbide innovation â including its pioneering work in LED technology and experience manufacturing high-purity semi-insulating (HPSI) wafers â Wolfspeed says that its optical-grade TSiC substrates are engineered for exceptionally low optical absorption and superior wafer flatness. Silicon carbide’s high refractive index, low birefringence, hardness and thermal conductivity make it a promising material for next-generation AR waveguides, supporting wider fields of view, improved image quality and more compact wearable devices. Beyond AR, TSiC technology offers potential in quantum computing, with the ability to host quantum bits (qubits), preserve their quantum states and transmit quantum information through light â all within a single silicon carbide crystal. Unlike many alternative materials, silicon carbide can support all these functions. “Wolfspeed’s leadership in silicon carbide innovation extends well beyond traditional semiconductor applications,” says Katrin Feurle, vice president, Beyond Power at Wolfspeed. “Our proprietary TSiC technology and extensive intellectual property portfolio position us to help enable breakthroughs in augmented reality, quantum computing and other emerging markets, reinforcing the versatility and transformative potential of silicon carbide,” he adds. “For years, the dream of truly immersive, all-day augmented reality glasses has run up against the hard limits of optical materials â you simply couldn’t get a wide field of view, high image quality, and a lightweight, wearable form factor all at once,” comments Barry Silverstein, a display systems and optics industry expert at the University of Rochester and former chief technology officer & senior director of Optics and Display Products at Meta Reality Labs. “Silicon carbide changes that equation. Its exceptionally high refractive index lets a single-layer waveguide do the work that previously took stacked optics, which is the kind of step-change the industry needs to move AR from a novelty into everyday eyewear. Wolfspeed's work on optical-grade TSiC technology is exactly the type of materials innovation that can finally unlock that potential.” Wolfspeed says that its technology is supported by a robust intellectual property portfolio. The firm continues advancing its 200mm optical-grade substrates while developing 300mm TSiC technology to support future market requirements. See related items: Wolfspeed agrees multi-year deal to supply 1200V silicon carbide devices to BorgWarner Wolfspeed adds Premium power substrates to 200mm silicon carbide portfolio Tags: Wolfspeed Visit: www.wolfspeed.com
News: LEDs 29 October 2026 Red GaN LED external quantum efficiency at 20.8% University of California Santa Barbara (UCSB) in the USA reports work on planar indium gallium nitride (InGaN) red micro light-emitting diodes (μLEDs) on sapphire substrates achieving peak external quantum efficiency (EQE) and wall-plug efficiency (WPE) of up to 20.8% and 13.2%, respectively [Roark Chao et al, ACS Photonics, online 7 October 2026]. The device also performed well at higher operating temperatures. The team comments: “In comparison to room temperature, we observe <8nm peak emission wavelength shift at 200°C operating temperature with less than 26% reduction in light intensity.” The EQE at 200°C was ~10%, “demonstrating a highly efficient and thermally resilient red InGaN/GaN μLED,” the team adds. The μLED featured an annularly mediated distributed Bragg reflector (DBR) for enhanced light extraction, and avoided complex growth sequences. Such devices are being developed for full-color IIIânitride displays and for visible light communication (VLC) applications. The LED material was grown by metal-organic chemical vapor deposition on c-plane GaN/patterned sapphire substrate (PSS) template (Figure 1). The five InGaN quantum wells (QWs) were separated by GaN layers grown at high (HT), medium (MT) and low (LT) temperatures. The well itself was capped with aluminium gallium nitride. AlGaN was also used as an electron-blocking layer (EBL). Figure 1: (a) LED epitaxy and fabrication scheme. (b) Scanning electron microscope (SEM) image of 60μm device. (c) Reflectance versus wavelength of sputtered DBR on silicon. The fabricated devices included indium tin oxide (ITO) transparent conductor for current spreading, and a 5-period DBR on the sidewalls. The reflector used sputtered silicon dioxide (SiO2) and tantalum oxide (Ta2O5) layers. The room-temperature turn-on voltage was 2.88V for 0.5A/cm2 current density. Under reverse bias down to â5V the leakage was less than 10â6A/cm2. The single peak emission wavelength was 619nm ‘red’ at turn-on. Increasing current blue-shifts the peak to shorter wavelengths, reaching 589nm ‘amber’ at 150A/cm2 injection. The full-width at half maximum of the peak was between 40nm and 70nm up to 150A/cm2, decreasing initially and reaching a minimum around 5A/cm2 and then increasing. Under increased temperature the peak wavelength tended to increase, around 7.5nm (606.8â599.3nm) at 50A/cm2 between 30°C and 200°C. The researchers comment: “This positions our spectral performance as superior to other IIIâV (e.g. AlInGaP) μLEDs, where a ~10nm wavelength shift has been reported for a smaller 120°C temperature increase.” The FWHM increased between 30°C and 200°C, going from 49.4nm to 58.6nm. Figure 2: (a) Maximum value-normalized light output versus current density for different temperatures. (b) EQE and (c) WPE versus log-scale current density. The peak EQE and WPE reached 20.8% and 13.2%, respectively (Figure 2). The team comments: “We attribute the EQE plateau at high current densities (i.e. excess of peak efficiency) to sequential quantum well injection and polarization-induced barriers at the GaN/InGaN interfaces.” Tags: Red LEDs AlGaN InGaN GaN Sapphire substrates Visit: https://doi.org/10.1021/acsphotonics.6c01611 The author Mike Cooke is a freelance technology journalist who has worked in the semiconductor and advanced technology sectors since 1997.
News: LEDs 29 October 2026 Seoul Viosys begins mass production of rare-earth-free white light emitter, with chips as small as 10µm For three decades, white LEDs have depended on rare-earth materials such as yttrium aluminium garnet (YAG) layered onto a blue LED chip (Figure 1). Opto-semiconductor device maker Seoul Viosys Co Ltd (SVC) says that it has now broken that dependence by developing and mass producing a chip that emits white light without rare earths. The chip can be as small as 10µm. Figure 1. New invention: white WICOP 3. Seoul Viosys and its parent company South Korean LED maker Seoul Semiconductor Co Ltd opened up the micro-LED market with WICOP (Wafer Integrated Chip on PCB), which is a chip architecture that eliminates the package altogether. With WICOP, the two companies have already developed and mass produced ultraviolet, blue, green, red and infrared LEDs smaller than 100µm in size. WICOP 3 is the third generation of the technology, extending that capability to white light without rare-earth elements (REEs). White LED market White LEDs comprise about $10bn of the $15bn global market for packaged LEDs. WICOP 3 can now replace them with a technology free of rare earths, reckons the firm. More significantly, WICOP 3 is claimed to be the world’s first white opto-semiconductor to achieve white light in a micro-LED smaller than 100µm. WICOP 3 uses neither rare earths (a major source of environmental pollution) nor a package. Nor does it contain synthetic silicone resins, plastics or lead frames used in conventional LEDs. The result is said to be a far more environmentally friendly product that costs about half as much to make as a conventional white LED. Creating new markets The miniaturized transistor replaced the vacuum tube and created vast new markets in electronics. The company believes micro white opto-semiconductors can do the same. WICOP 3 generates white light from gallium nitride (GaN) alone. Also, the chip contains no plastics, silicone or other synthetic organic materials. It can hence last for decades. In lighting, invisible micro-emitters could be embedded in wallpaper or window glass, lighting a space with no fixtures at all. This would end the inconvenience of replacing bulbs and the high cost of fixtures. The company expects this to create a new market tens of times larger than today's $10bn white LED market. Performance In its first mass production, a micro-LED chip measuring just 25µm x 10µm produced 0.015lm of white light. Its chromaticity falls inside the CIE standard white region (Figure 2). Luminous efficacy is already close to 100lm/W. The company aims to reach 200lm/W within two years. A conventional 1000µm x 1000µm chip achieves 50lm. Figure 2. WICOP 3 brightness by size. Technical significance Up to now, WICOP could make chips smaller, but white light still required a package containing rare earths. White chips therefore could not go below 1000µm. This held back cost reduction. White micro LEDs under 100µm (0.1mm) were also out of reach. Removing rare earths changes that. White light is now possible both in large chips of 1000µm and above and in micro LEDs below 100µm. Future plans Seoul Group (consisting of Seoul Semiconductor and Seoul Viosys) will start mass production of WICOP 3 in fourth-quarter 2026. It says it will supply first those customers that have respected its intellectual property and relied on its products. Seeking supply chain partners Seoul Viosys uses WICOP to produce micro-emitters smaller than 100µm. Micro-LEDs built on WICOP can now carry high volumes of AI data over distances from under 1cm to tens of meters. Over short distances, data has long traveled electrically through copper wire. Under the data loads of the AI era, copper links slow down, generate heat and consume much more power. Using light instead, Seoul Viosys arranges 1000 WICOP chips of about 10µm each in a grid within an area of 1mm2 or less. This array transmits data 10 times faster at one tenth of the power. Market research firms including Omdia forecast that this technology and augmented reality (AR) together will create a new $60bn market within five years (equal to half of today's DRAM memory market). Seoul Semiconductor’s founder Chung Hoon Lee says that the company intends to target WICOP 1, 2 and 3 at applications in AR glasses and AI data communications. These technologies work on scales of 10µm or less. To that end, it is seeking trusted upstream and downstream micro-LED supply chain partners in AR displays and AI transmitters. See related items: Seoul Viosys expanding business beyond components to data-interconnect transceivers Tags: Seoul Semiconductor Visit: www.seoulviosys.com Visit: www.SeoulSemicon.com
The semiconductor industry crossed $1 trillion in annual revenue this year, almost four years ahead of earlier projections. SEMI President and CEO Ajit Manocha opened the CEO Summit at SEMICON West with a chart that told the story. A year ago, the forecast for 2030 was $1 trillion. Now it is $2 trillion, with $3 trillion possible by 2035. The industry has 102 new fabs coming online through 2029 and needs more than 50 beyond that by 2035. Money and capacity won’t carry that growth alone. Synopsys CEO Sassine Ghazi named the shortage of engineers as the industry’s challenge. Brooks Automation CEO Dave Jarzynka pointed out that a wafer spends only about 25% of its time in the fab actually being processed. AMD’s Justin Murrill summed up the mood in two lines: “Constraints don’t prevent progress. They guide where the next breakthrough comes from.” The question underneath it all was how to deliver more, faster, with the people and factories we have. I spent Tuesday, October 13, in Room 20 at Moscone North for the design session, “Bridging Design and Manufacturing with AI,” and it took that question on directly. Speakers from TSMC, Intel, Applied Materials, Lam Research, Cadence, Silvaco, PDF Solutions, McKinsey, Cerebras, SanDisk, and VerifAIX covered everything from atoms to agents. Seven themes stood out: AI is expanding the solution space AI’s real payoff is faster learning, not cost reduction AI is compressing the steps, and the time between them is the next frontier Co-optimization is replacing the sequential handoff Design is speeding up, manufacturing is not Autonomous design is causing trust issues Digital twins are changing how development gets done AI is expanding the solution space. Lam Research’s David Fried put the number of possible process recipes on the order of 10²³. Intel’s Vikas Sharma showed a design-technology co-optimization (DTCO) search space that grew from fewer than 10 options to more than a million. Applied Materials’ Subi Kengeri described thousands of materials candidates and hundreds of coupled variables per study. No team of engineers can explore that many options on their own. ML finds the parameters that matter, and AI finds the best candidates to try. AI’s real payoff is faster learning, not cost reduction. Sandisk said it plainly on the IEEE panel moderated by Silvaco’s Wally Rhines: AI narrows ten candidates to three before design starts, with fewer experiments and shorter cycles, and the value is speed. Intel’s DTCO decisions dropped from weeks to one or two hours. Applied Materials cut a 3D gate-all-around device simulation from 20.5 days to 19.7 hours on GPUs. Every one of these is a learning loop getting shorter. AI is compressing the steps, and the next frontier is the time between them. Cycle time inside the steps is falling fast. McKinsey showed AI-assisted programs reaching tape-out nine months after design starts and cutting debug closure time by 40%. TSMC’s agentic place-and-route runs around the clock at 3 to 5x productivity. McKinsey’s Aaron Aboagye added a related point: a meaningful share of development latency is organizational, not physical, and orchestration compresses the white space between technical steps. PDF Solutions showed test data that rarely follows the product downstream. Brooks’s 25% is the same pattern in the fab: most of a wafer’s time is spent between the steps, not in them. I’d take McKinsey’s point one step further. As AI compresses the time inside the steps, the time between them, team to team and team to tool, becomes a bigger share of the schedule. From inside a program, that time has a cause: how the work between the steps is designed. In most programs, it was never designed at all. Co-optimization is replacing the sequential handoff DTCO, and system-technology co-optimization (STCO) says the same thing: design, process, package, and system decisions get made together, not passed down a line. Applied Materials described STCO as one coupled loop, with constraints flowing down and outcomes flowing up. Intel showed that degrees of freedom and reversibility shrink as the PDK matures, so the right decisions must come early. Cerebras showed co-optimization at wafer scale, engineering the wafer, DRAM, and optics together and coupling every design domain. TSMC is moving from the PDK to an AI Design Kit built for agents. McKinsey called for persistent, cross-stack co-development in place of sequential handoffs. System complexity keeps rising, and engineers have had to rise with it. Technical depth used to be enough. Then we needed breadth. Now we need to understand the whole system. Co-optimization is the latest answer to that pressure, and as complexity grows, it will have to keep evolving. Design is speeding up; manufacturing is not. Manufacturing can’t iterate without physical consequences, and the physics keeps getting harder. Transistors have gone from planar to FinFET to gate-all-around, with CFET and 2D materials next. Rhines showed NAND process steps rising from about 400 to as many as 1,800, wafer lot cycle time stretching from 8 to 10 weeks at 28nm to 16 weeks or more, and mask sets climbing from $1 to 3 million to $20 to 40 million or more. McKinsey’s view: manufacturing remains largely uncompressed. Autonomous design is causing trust issues. VerifAIX’s Madhulima Tewari called it the correctness gap. She cited first-silicon success at 14% and the best AI pass rate on hardware code generation at 34% and argued that the system that generates an artifact can’t be the only one that certifies it. Her answer: the LLM proposes, deterministic engines decide. Cadence’s Jeff Roane said agentic AI is here now, with one to two years to figure out how to use it well. At the CEO Summit, Ghazi described the end state: you give an outcome, not a prompt, and human judgment still defines the architecture. Digital twins are changing how development gets done. Systems are getting harder for any one engineer to understand, which is why digital twins are becoming so important. Models and virtual prototypes help development teams see how the pieces interact. Physical prototypes teach the same lessons, but every learning cycle on silicon costs weeks and millions of dollars. Rhines called the virtualization of manufacturing inevitable. Physics simulation trains surrogate models that let teams test process changes before running a wafer. Lam builds virtual twins of process and fab, and Applied Materials uses the same surrogate pattern from materials to system. The twins run on data, and the data is exploding. PDF Solutions’ Kimon Michaels cited Qualcomm’s engineering and manufacturing data growing 600% since 2022, while less than 5% of manufacturing data gets analyzed. A twin is only as good as its calibration. Across all seven themes, the pattern was the same: AI is making each step faster and each search smarter. Lam’s own research, published in Nature, put the lesson plainly: engineers and algorithms working together, with the handoff in the right place, cut the cost of reaching a process target in half. That handoff is a design decision, and so is every other boundary in the flow, between design and manufacturing, between teams, between companies. When an agent can run place-and-route around the clock, your schedule stops being set by how fast your engineer works. It is set by how fast decisions, data, and learning move across those boundaries. The $1 trillion was built on faster tools. The next trillion goes to the companies that design how their people and tools work together. Also Read: Accellera’s FSL 1.0 Gives Functional Safety Data a Common Language SEMICON West 2026: After the Toast, the Hard Questions WEBINAR: Cut down EDA License cost by 25% with Stratos AI Nitro Share this post via:
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Samsung Electronics Posts $80B Operating Profit on AI Memory Demand
Smarter Power Sequencing with GreenPAK™
Extends proven low-power leadership by cutting down power consumption by half, achieving top ULPMark®-PeripheralProfile benchmark scores, and increasing reliability with ±4 kV HBM ESD tolerance. Expands the existing RL78/G23 lineup with expanded touch-key functionality for advanced HMI devices, along with enhanced security. Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced the RL78/G21, a new member of its RL78 family. Renesas holds the No. 1 global market share in 16-bit MCUs (Note 1). The RL78/G21 MCU extends that leadership into the next generation of smart appliances. Optimized for smart system control, the new MCU product series RL78/G21 combines a low-power design with optimized peripheral functions enabling both energy savings and lower costs in system-control applications such as air conditioners, refrigerators, washing machines and microwave ovens. Renesas also expanded its existing RL78/G23 lineup with new devices featuring additional capacitive-touch channels to address demand for more advanced HMI devices. Together, the RL78/G21 and RL78/G23 provide flexible design options: RL78/G21 optimized for efficient system-control, while RL78/G23 integrates system control and user-interface functions into a single MCU, helping reduce system BOM costs. Ensuring Reliability, Security and Flexibility in Smart Appliances For more than 15 years, the RL78 family has earned the trust of customers worldwide across a broad range of applications. The new RL78/G21 and RL78/G23 strengthen that foundation forward with enhanced security capabilities that help protect against physical threats, such as counterfeiting and cloning, as well as cyber threats, including unauthorized access, information leakage, tampering and spoofing. The RL78/G21’s high electrostatic discharge (ESD) tolerance of ±4 kV HBM contributes to higher reliability throughout manufacturing and assembly, as well as during operation of the end product. The RL78/G21 also adds the UARTA communication interface, an upgrade over the RL78/G13, enabling flexible system expansion such as the addition of sensors. Because RL78/G21 is pin and function compatible with the existing RL78/G13 and RL78/G23, customers can transition designs seamlessly to the new devices with minimal redesign effort. Ultra-Low-Power MCU Optimized for System Control The RL78 family has demonstrated its ultra-low-power capabilities with products achieving top scores in the ULPMark®-PeripheralProfile benchmark. Leveraging the advanced low-power technologies developed for the RL78 family, the RL78/G21 achieves an operating current of just 34 μA/MHz, nearly half that of the leading RL78/G13 MCU products. This helps reduce battery capacity, downsize power supply circuits and lower overall system costs. Optimization for system control also gives the device strong price competitiveness in the class of products with 128KB or 256KB of code flash memory. The integration of a high-speed on-chip oscillator (HOCO) with ±1.0% accuracy and 4KB of data flash eliminates the need for an external oscillator and EEPROM, reducing BOM costs. Scalable Touch HMI Support As demand for touch input grows with the increasing sophistication of human-machine interfaces (HMIs), Renesas expanded the RL78/G23 lineup with the RL78/G23 (R7F104G), which offers enhanced capacitive-touch sensing. Compared with the existing RL78/G23 (R7F100G), which provides 14 touch channels in the 44-pin version and 16 touch channels in the 48-pin version, the new devices significantly increase the number of touch channels to 24 and 25, respectively. Renesas provides common touch peripheral functionality and the QE for Capacitive Touch tool across the RL78, RX and RA families, enabling scalable HMI development ranging from simple user interfaces to advanced graphics displays. “The RL78/G21 and RL78/G23 are built on the proven strengths of the RL78 family, delivering significant advances in low-power performance, reliability and security,” said Raji Mukhopadhyay, Business Division Manager, EP Mainstream MCU Business Division at Renesas. “The RL78/G21’s ±4 kV HBM ESD tolerance is a key differentiator. It further strengthens reliability, while its enhanced security capabilities address the growing need for more secure smart appliances.” Additional Features Self-diagnostic functionality enabled by an IEC 60730-compliant self-test library Security features including flash read protection, flash shield window, Unique ID and Customer ID High ESD tolerance of ±4 kV HBM (Human Body Model) (RL78/G21 only) Pin and functional compatibility with the existing RL78/G13 and RL78/G23 Wide operating voltage range from 1.6V to 5.5V Development support through Smart Configurator and the Fast Prototyping Board (FPB) “Appliance makers are asking for more intelligence, better user experiences and stronger security without increasing cost or energy consumption,” added Mukhopadhyay. “With the RL78/G21’s ultra-low-power performance and enhanced security, alongside the RL78/G23’s expanded touch capabilities, customers can select the right MCU for their system-control and HMI requirements and bring more efficient, reliable and secure smart appliances to market faster.” About Renesas Electronics Corporation Renesas Electronics Corporation (TSE: 6723) empowers a safer, smarter and more sustainable future where technology helps make our lives easier. A leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live.