Tech news in 3 minutes

Netlist Expands Legal Action Against Samsung and Google for Infringement of New AI Memory Patents

19 d ago

Amid rising DRAM prices and extended delivery lead times, Meta has disclosed a memory-reuse strategy that repurposes DDR4 modules from decommissioned servers rather than disposing of them. The approach, detailed by Meta researchers, expands server memory capacity without purchasing new DRAM, bypassing what industry observers call the “RAM tax”—the elevated cost burden hyperscalers face due to tightening memory supply. The expansion is enabled through CXL (Compute Express Link) technology, which connects older DDR4 modules alongside newer DDR5 memory pools within the same machine. Instead of retiring DDR4 DIMMs when servers are decommissioned, Meta pools that capacity and makes it addressable as expanded memory attached via CXL to newer server fleets. Meta describes the result as delivering near-zero-cost memory expansion while cutting electronic waste and reducing the emissions footprint of its infrastructure. The timing aligns with ongoing memory supply constraints affecting server deployment schedules globally. Meta’s researchers noted that prior CXL memory-expansion implementations were impractical at hyperscale due to three constraints: CXL delivered roughly ten times lower bandwidth than local directly-attached memory; latency was about 60% higher; and commercially available CXL products bundled the controller with the DRAM module, blocking reuse of existing DDR4 inventory. To overcome these, Meta designed a custom ASIC named Vistara, engineered for low latency, power efficiency, and reuse of recycled memory, decoupling the controller from the DIMMs. A software layer built on TPP (Transparent Page Placement) automatically determines the right ratio of local to expanded memory for each workload and can disable expanded memory for latency-sensitive tasks. Meta deployed this model for disaggregated ML inference and distributed caching—a hot topic given Meta’s history with Memcache. For these applications, total RAM capacity is more important than memory speed, as cache misses are the primary concern.