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From Tokens to Infrastructure: Why Compute, Memory, and Power Will Determine the Future of AI

21 d ago

For the past decade, the semiconductor industry has pursued "shift-left" verification, moving validation into the pre-silicon phase using virtual platforms, emulation (e.g., Synopsys ZeBu, HAPS), and FPGA prototyping to boot OS and run applications months before tape-out. This software-driven approach worked well for predictable mobile workloads but is now breaking down due to two trends. First, AI infrastructure lacks a representative workload. Every model, framework, and deployment stresses architectures differently, making software-driven validation insufficient for complete confidence. Second, modern SoCs are tightly integrated platforms where CPUs, GPUs, NPUs, memory hierarchies, and accelerators interact, creating bugs that emerge from inter-block interactions—coherency conflicts, race conditions, and timing-dependent failures—often requiring billions of cycles to appear. Real software rarely triggers these pathological conditions, so coverage and realism compete. The industry is rediscovering synthetic stress: intentionally generating instruction streams that push hardware into extreme states (heavy contention, rare coherency scenarios) to expose weaknesses real software misses. However, executing enough such tests requires scale beyond simulation. Hardware-assisted platforms like ZeBu and HAPS are now essential for exploring deep system behavior at emulation speed. The emerging model shifts from running software to systematic system exploration via automated test generation. Tools like Synopsys' Threadmill for Arm and STING for RISC-V, combined with Imperas reference models, enable continuous verification flows spanning RTL verification through emulation and prototyping. Workloads evolve across stages, improving coverage and reducing fragmentation. This continuity—connecting early test generation with hardware-assisted execution—is key to addressing modern verification challenges.