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Semiconductor Engineering Has a State-Continuity Problem
CAST has introduced TCPIP-100G, a synthesizable intellectual-property core that implements a complete TCP/IP stack in hardware for ASICs and FPGAs, enabling autonomous 100 Gbps transmission and reception without host processor dependency. This core handles connection management, retransmission, flow, and congestion control entirely in hardware, supporting up to 32,768 simultaneous sessions configured at synthesis time. It operates as client or server, with base features including IPv4, ARP, ICMP, VLAN tagging, checksum generation, and jumbo frames. Options add DHCP client, out-of-order reassembly, UDP stack with IGMPv3 multicast, and a separate path for other IP traffic. Designers can choose cut-through mode for low latency or store-and-forward for integrity. Integration uses AXI4-Stream, AXI4-Lite/APB3, and AXI4 external memory interfaces, with independent clock domains. The core is independent of external memory technology, MAC, and PHY, and deliverables include synthesizable Verilog RTL or FPGA netlist. By offloading the full TCP stack to dedicated logic, TCPIP-100G makes latency more deterministic, frees CPU cores, and reduces data movement overhead—critical for AI/HPC clusters, hyperscale infrastructure, SmartNICs, and NVMe-over-TCP storage. While implementation results (area, frequency, power, throughput) are not yet published, the core represents a shift from software-based networking to a configurable hardware building block. Source: CAST, September 8, 2026.