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Feed Forward Intelligence: Enabling Testability in the Chiplets Era

33 d ago

Caspia Technologies will host an upcoming webinar addressing the growing threat of chip-level security vulnerabilities. The event, previewed in a recent dry run, features two key presentations and a live demo aimed at helping engineers build attack-resistant chips. Beau Bakken opens the webinar with an overview of the threat landscape, warning that AI agents are autonomously discovering and exploiting vulnerabilities at machine speed. He then explains how Caspia’s static RTL checking tool, CODAx, integrates security verification and repair into existing design flows. Newly released features include Asset Assist, which automatically identifies security-critical assets without manual annotation, and Report Assist, which summarizes complex violation reports to help prioritize high-risk issues. Dr. Zahin Ibnat follows with a hands-on security analysis demo using the Caliptra open-source root-of-trust design. She shows how CODAx identifies security issues in the design and demonstrates the flow’s ease of use, allowing any engineer to apply expert-level analysis. The demo highlights how Asset Assist reduces reliance on security experts and provides guided remediation. Multiple examples of violation detection and fixing are presented, with a deep dive into four specific cases. The webinar emphasizes that chip-level vulnerabilities are an existential threat for virtually all systems, and that security fixes must be implemented before AI-driven attacks accelerate. Caspia encourages all complex chip designers to attend. A registration link is provided for those interested.

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