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NVIDIA and Mediatek Ink $3.5B Investment Deal, Accelerate NVLink Fusion Adoption
NVIDIA outlined its roadmap for integrating RISC-V as a host CPU option in its GPU platforms at Hot Chips 2026, detailing the requirements for running CUDA and NVLink Fusion on RISC-V server processors. The presentation focused on how RISC-V CPUs must meet specific specifications—including RVA23 profiles, ACPI 6.6 support (ratified May 2025), and the RISC-V Boot and Runtime Services specification (August 2025)—to achieve software binary compatibility with NVIDIA’s accelerated computing stack. CUDA applications split work between CPU and GPU modules, requiring complex host software that already supports x86 and Arm. For RISC-V, NVIDIA emphasized PCIe I/O coherence and peer-to-peer communication as critical CUDA-specific requirements to avoid cache flushes and enable direct GPU-to-GPU data transfers. The NVLink Fusion platform, which connects custom silicon to NVIDIA’s AI ecosystem, adds further demands: a high-speed C2C interconnect with ~88 PCIe lanes, CHI coherence, and software like DOCA and NCCL. SiFive was named as the RISC-V-based NVLink Fusion CPU partner. NVIDIA’s Vera Rubin full-stack AI factory platform, spanning seven chips and five racks, was also showcased, with the NVL72 rack packing a 72-GPU L1 domain using NVLink Fusion chiplets and Vera CPUs. The company argued that RISC-V’s open standard, multiple vendors, and customization capabilities make it a genuine third server CPU option alongside x86 and Arm. While broader deployment is still two generations away, NVIDIA confirmed it has concrete plans for RISC-V in its platforms, moving beyond current low-level controller use to host CPU roles.