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Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late

32 d ago

IP-XACT has become a cornerstone standard for complex SoC design flows, evolving from 2009 through 2014 to the 2022 revision. Its adoption, whether driven internally or imposed by customers and providers, is now a reality. However, IP-XACT presents significant challenges: its XML-based structure is not human-readable, objects have dense interdependencies, and different organizations develop "flavors" that cause interoperability friction. More critically, IP-XACT must remain consistent with other design representations like RTL, SDC, and register specifications; any error can silently propagate across the design flow. Design teams need a platform that supports all major IP-XACT versions, abstracts complexity, enables productive manipulation, and guarantees consistency with RTL. Defacto Technologies offers SoC Compiler, an EDA tool that efficiently supports IP-XACT design flow for RTL teams, making IP integration easier. Their webinar on June 24th from 10–11 AM PDT covers pitfalls of IP-XACT, the ideal IP-XACT platform, and SoC Compiler's role in the EDA tool flow. With SoC Compiler, teams can design using IP-XACT, RTL, or both, keeping databases synchronized and eliminating errors. Attendees will learn to check IP-XACT/RTL consistency, generate missing views, package and insert IPs, connect IPs, generate top-level views, report connectivity, extract and check system-level memory maps, and generate documentation. Users can also use APIs to create, query, or edit IP-XACT, with support for advanced capabilities like the Tight Generator Interface (TGI). Defacto's AI Assistant aids tool adoption and reduces required IP-XACT expertise. Speakers are Chouki Aktouf (CEO/CTO) and Olivier Florent (Technical Expert). Target audience includes design teams integrating internal and third-party IP cores, RTL designers, SoC design architects, and design verification engineers.