Tech news in 3 minutes
GPU-native mask rule checking eliminates the curvilinear mask rule check bottleneck
At the 2026 VLSI Symposium, Intel Foundry provided an update on its process technology roadmap, focusing on the maturation of Intel 18A, the introduction of Intel 18A-P, and advanced research beyond gate-all-around (GAA) transistors. Intel’s strategy combines manufacturing execution with differentiated technologies to strengthen its foundry position. Intel 18A, featuring RibbonFET GAA transistors and PowerVia backside power delivery, is now ramping in two U.S. fabrication facilities, with defect density declining ahead of projections. It is already powering multiple client products, with data center applications expected soon. Intel 18A-P, the first performance-enhanced derivative, introduces new transistor options, improved power delivery, and enhanced thermal characteristics while maintaining backward compatibility. Based on a fully routed Arm core test vehicle, it offers up to 18% lower power consumption at iso-performance and about 9% higher performance at iso-power. Thermal resistance improves by 20–40%, and via resistance on critical interconnect layers decreases by 10–30%. A dual-contact Power Boost structure combines front-side and backside contacts via PowerVia to reduce parasitic resistance and improve current delivery. New intermediate threshold-voltage (Vt) options provide design flexibility, with 33% tightening of skew corners and reduced process variation. Thermal management innovations include enhanced conductivity and EDA-driven optimization for power-dense AI and HPC workloads. Combining backside power delivery with GAA transistors yields approximately 10× dynamic voltage droop reduction, 5–6% frequency improvements, or over 15% dynamic power reduction, plus routing simplification and area efficiency. Beyond current production, Intel presented research on Complementary FETs (CFETs) stacking PMOS and NMOS vertically, with a monolithic CFET inverter at 45 nm contacted poly pitch. A ruthenium-based interconnect architecture with air-gap integration achieved about 35% capacitance reduction versus copper. Additionally, integration of gallium nitride (GaN) power devices with silicon CMOS logic on 300 mm wafers aims to improve system efficiency and reduce cost. Collectively, these announcements highlight Intel Foundry’s dual focus on near-term manufacturing execution (18A ramp, 18A-P performance boost) and long-term innovation (CFETs, advanced interconnects, heterogeneous integration), positioning Intel as a leading developer of next-generation semiconductor process technologies.