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Cornelis and NextSilicon announced at ISC High Performance 2026 a collaboration to develop and evaluate joint reference architectures for AI and HPC. The effort pairs Cornelis’s CN5000 congestion-free fabric (400 Gbps, launched in 2025) with NextSilicon’s Maverick-2 compute platform (volume shipments began late 2025), targeting two key infrastructure bottlenecks. On the network side, standard Ethernet struggles with latency-sensitive messages from AI inference and HPC simulations, causing congestion and idle compute time; the CN5000 eliminates that wait. On the compute side, the traditional von Neumann model stalls on irregular, data-dependent workloads; Maverick-2 uses Intelligent Compute Architecture (ICA), a software-defined dataflow design that reconfigures at runtime without code modification. The first phase validates performance combinations for OEM partners, providing proven blueprints instead of untested parts lists. Plans extend testing to the 800 Gbps CN6000 fabric due in the second half of 2026. “Operators keep telling us their most expensive systems sit idle, waiting on the network,” said Lisa Spelman, CEO, Cornelis. “We built the CN5000 to end that wait.” Elad Raz, founder and CEO, NextSilicon, added: “For decades, software had to bend to fit the processor. Maverick-2 makes the processor adapt to the software.” Future work will target emerging AI workloads, including disaggregated inference for Mixture of Experts (MoE) models and agentic AI, where the fabric becomes part of the compute path. As CN6000 becomes available, the companies will evaluate how a congestion-free fabric and reconfigurable compute support these patterns, with findings intended to inform future OEM reference designs.